1. Technical Field of the Invention
The present invention relates, generally, to a method for cleaning a processing chamber used for manufacturing a semiconductor device and a method for manufacturing the semiconductor device by employing the same. More particularly, the present invention relates to a method for cleaning a processing chamber by removing impurities on a semiconductor substrate and in the processing chamber before employing a chemical vapor deposition process, and a method for manufacturing a semiconductor device by employing the same.
2. Discussion of the Related Art
As semiconductor devices become more highly integrated, the design rules, for example the channel lengths of transistors, the intervals of active regions, the widths of wirings, the intervals of wirings, and the sizes of contact holes, have been reduced. Therefore, the aspect ratio of a contact hole formed on a semiconductor substrate has gradually increased. The aspect ratio of the contact hole indicates a ratio of a depth of the contact hole relative to the diameter of the contact hole.
In the conventional interconnecting wires and films using aluminum (Al) deposited by a sputtering process, there are several disadvantages. For example, the contact resistance of the wiring or the connecting film may increase in accordance with the high degree of integration of a semiconductor device while the step coverage of a deposited film may deteriorate. Thus, the wiring and the connecting films may be more easily broken at the windows of the contact holes. Also, the connecting film using aluminum (Al) may also be more easily broken due to electro-migration during operation of a semiconductor device.
Considering the above-mentioned problems, there are various metal plugs for electrically connecting a conductive layer to an underlying conductive layer. In this case, a contact hole is formed through an interlayer dielectric film interposed between an upper and a lower conductive layers, and then a metal plug fills the contact hole to electrically connect the upper conductive layer to the lower conductive layer.
Generally, a metal plug including tungsten (W) has good step coverage, and is formed using a plasma enhanced chemical vapor deposition (PECVD) process.
FIG. 1 is a cross-sectional view illustrating a semiconductor device including contact holes. In FIG. 1, metal plugs are formed in contact holes by a deposition process after the contact holes are formed through an interlayer dielectric film 30.
Referring to FIG. 1, an active region and a field region 15 are defined in a semiconductor substrate 10, and then the interlayer dielectric film 30 is formed on the substrate 10.
Source/drain region 20 having predetermined patterns is formed in the substrate 10 beneath the interlayer dielectric film 30. The source/drain region 20 is formed by using an ion implantation process in which dopant atoms are implanted into the substrate 10.
A metal silicide film 22 is formed on the semiconductor substrate 10 to improve the electric conductivity between the source/drain region 20 and a metal plug 50. A contact hole is formed through the interlayer dielectric film 30 by an etching process to expose the metal silicide film 22.
Then, titanium (Ti) 40 and titanium nitride (TiN) 45 films are deposited on the interlayer dielectric film 30 including the contact hole. The titanium film 40 and the titanium nitride film 45 serve together as a barrier layer. The titanium film 40 is formed in the contact hole and on the interlayer dielectric film 30 by a chemical vapor deposition (CVD) process or a sputtering process, and the titanium nitride film 45 is formed on the titanium film 40 by a CVD process or a sputtering process. In addition, to form the metal plug 50, tungsten is deposited in the contact hole and on the titanium nitride film 45.
Further, the metal silicide layer 22 is formed on the source/drain region 20 to reduce the contact resistance between the metal plug 50 and the source/drain region 20. That is, the metal suicide layer 22 serves as an ohmic layer to reduce the contact resistance between the source/drain region 20 and the metal plug 50. Also, the metal silicide layer 22 works as a diffusion barrier layer that can prevent materials from mutually diffusing between a metal layer and a semiconductor substrate or between two metal layers of a multi-layered construction.
The metal silicide layer 22 generally includes metal silicide such as titanium silicide (TiSi2), platinum silicide (PtSi2), palladium suicide (PdSi2), cobalt silicide (CoSi2), or nickel silicide (NiSi2). Because the cobalt silicide is stable at the high temperature of about 900° C., a doped glassy film for planarization can be sufficiently formed on the cobalt silicide. Additionally, because the cobalt silicide has a low resistance of about 16 to about 18 μΩ·cm, the suicide cannot be extended on the semiconductor substrate along the horizontal and the vertical directions. Furthermore, the cobalt silicide can be selectively etched, but not excessively etched during a plasma etching process in comparison with the titanium silicide.
However, a native oxide film may be easily formed on a cobalt silicide as compared to a titanium silicide such that the oxide film creates a barrier between the cobalt silicide and metal formed thereon. In other words, the cobalt silicide may have poor electrical contact relative to the metal formed thereon due to the oxide film. Thus, the surface of the cobalt silicide layer should be cleaned by a cleaning process.
FIGS. 2 and 3 are sectional views illustrating the conventional method for forming a tungsten plug.
Referring to FIG. 2, after a passivation layer 24 including a photoresist or an oxide is formed on a semiconductor substrate 10, the passivation layer 24 is partially etched in accordance with a predetermined pattern, thereby exposing predetermined region of the substrate 10, for example, a source/drain region.
Dopant atoms are implanted into the exposed region of the substrate 10 such that the source/drain region are formed on the substrate 10. The metal for forming a metal silicide film 22 is then deposited on the source/drain region by a chemical vapor deposition (CVD) process or a sputtering process. The metal reacts with silicon at a high temperature so that the metal silicide film 22 is formed on the source/drain region. Preferably, titanium (Ti) or cobalt (Co) may be employed to form the metal silicide film 22. The titanium or cobalt reacts with the silicon of the substrate 10 to form a titanium silicide (TiSi2) film or a cobalt silicide (CoSi2) film.
Referring to FIG. 3, after the remaining passivation layer 24 is removed, an interlayer dielectric film 30 is formed on the semiconductor substrate 10 including the metal silicide film 22 formed thereon.
A photoresist pattern for forming a contact hole 32 is formed on the interlayer dielectric film 30 by a photolithography process, and then the source/drain region is exposed through an etching process, thereby forming the contact hole 32. In this case, an oxide film 34 may be formed on the metal silicide film 22 exposed through the contact hole 32 after the etching process for forming the contact hole 32 is performed. In addition, impurities including etched by-products may exist on the metal silicide film 22. Because the semiconductor substrate 10 generally goes through several manufacturing processes to complete a semiconductor device, the semiconductor substrate 10 may come into contact with the surrounding atmosphere when the semiconductor substrate 10 is transferred from one processing chamber to another processing chamber. At that time, the oxide film 34 may be formed on the substrate 10 when the substrate 10 comes into contact with the surrounding atmosphere. Though a minute oxide film 34 is interposed between the source/drain region 20 and the metal plug 50, the electrical contact between the source/drain region 20 and the metal plug 50 is poor.
Accordingly, the oxide film 34 and the remaining impurities in the contact hole 32 should be removed from the substrate 10 before depositing other films for forming the plug 50 in the contact hole 32. The process for removing the oxide film 34 and remaining impurities is called a pre-cleaning process.
The pre-cleaning process has been provided to remove oxide films and other impurities from the substrate before employing a CVD process for depositing titanium and titanium nitride films. For example, in Unity-EP (manufactured by Tokyo Electoron Co. in Japan) for depositing a titanium/titanium nitride film employing a CVD process, the titanium/titanium nitride film is deposited after the pre-cleaning process is executed. When the metal silicide film includes cobalt silicide, the substrate is generally pre-cleaned with a discrete apparatus by employing a radio frequency (RF) plasma etching process ex-situ, and then the pre-cleaned substrate is transferred to a processing chamber for performing a CVD process.
In addition, the Unity-EP may have an additional function by installing a adequate processing module. Also, the Unity-EP can perform the pre-cleaning process in-situ by installing a Pre-Cleaning Etching Module (PCEM) therein. When the pre-cleaning is executed in-situ, the processing time can be reduced, and the throughput can be improved.
In the conventional pre-cleaning method, a plasma etching process is performed in a processing chamber with an argon (Ar) gas. However, when the pre-cleaning method is performed with the argon gas through a dry etching process, several disadvantages may occur as follows.
FIG. 4 is an enlarged cross-sectional view showing the surface of the source/drain region in FIG. 3.
As shown in FIG. 4, the metal silicide film 22 is damaged when the RF plasma etching process is excessively performed with the argon gas. In other words, the conventional methods remove the metal suicide layer 22 with an oxide film and other impurities during the RF plasma etching process.
It is very difficult to precisely control the RF etching process without etching the metal silicide film 22. Also, the time may be disadvantageously increased when the etching process is executed by controlling the amount of the metal silicide film 22 to be etched. Furthermore, the manufacturing cost of a semiconductor device is increased while the yield of the semiconductor device is reduced. In fact, the cobalt silicide film is removed with the oxide film and the impurities at an identical rate as the oxide film and the impurities are removed from the substrate during the etching process. As a result, processing failures are caused due to the loss of the cobalt silicide film.